How Modern CPUs Work at ASE Labs

»How Modern CPUs Work at »ASE Labs

Modern CPUs are increasingly more and more complex and it seems there is no end in sight. Let's take a look at a generic modern day CPU and see how it works.

This seems more like an excerpt (especially the diagrams) or, at best, the author's revision notes on the Computer Organisation and Design - The Hardware/Software Interface textbook by Patterson & Hennessy (2nd ed.).

It *is* a very good book, basing its approach on the very rational MIPS instruction set, looking at multi-cycle implementations, pipelining, memory hierarchy, etc. I understand that the new edition studies newer (well, currently prevalent) CPU architectures. If you really are interested, buy it or find it in a library.

-Tez

Don't be so quick to judge like that. I attended the class, never read the book. Since I have gained knowledge from it and now understand the material, it comes from my memory of the subject, not from a textbook.

I have edited the article to give where I took the slides from, though.

It's a nice article, but lacks depth at times. For example you give no explanation why the clock speed is increased for multi-stage pipeline or how the CPI variations are calculated. Also the latter diagrams seem inconsistent with the scope and the first diagrams of the article.

You're correct about the CPI determination, I pulled that out of a hat. That was for explination purposes only (in regards to branches and other pipeline stalls). I did explain why the clock speed increased for a pipelined CPU.

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In a multi-cycle CPU, the clock speed is set for the longest amount of time one stage of the pipeline takes. In the laundromat example, it would set at 40 minutes since that is the longest stage in the datapath.